Silicon Architect

ABOUT NORMAL COMPUTING Normal Computing builds silicon that turns thermal noise from an obstacle into a computational resource. Conventional chips spend most of their energy forcing determinism onto physics; ours compute with it. Stochastic, in-memory, asynchronous: the result is 10-100× more AI inference per dollar, per watt. We co-design the full stack: AI-native EDA systems in production with the world's largest semiconductor companies, and the advanced ASICs they make possible. Backed by $85M+ from the world's leading deep-tech investors and built by scientists, engineers, and operators from the labs that built modern computing. Normal works as one team across New York, Silicon Valley, London, Copenhagen, and Seoul. We hire people who want the hardest version of their craft, across every discipline, at every seniority. THE ROLE Most accelerator architecture is refinement: a known substrate, a known programming model, decades of prior art to lean on. This seat is not that. Normal's silicon computes with stochastic analog dynamics in memory, and the architecture that exploits it is being discovered alongside the work. As our Silicon Architect, you will own the architecture of its compute blocks: the core decisions that determine how Normal's silicon actually computes, working directly with our Systems Architect, research and engineering leadership, and the AI platform team whose tools you'll use to design it. This is a seat for someone who wants to define structures no prior art covers, and who has the architecture-to-silicon range to defend them all the way to tapeout. WHAT YOU'LL OWN - Compute Architecture: Help define the architecture and microarchitecture of novel AI accelerator compute blocks: PE array design, datapath organization, and support for efficiency techniques such as sparsity exploitation and reduced-precision computation. The compute tile is the surface where Normal's research advantages have to show up in silicon, and you are one of the people responsible for making sure they do. - Workload-to-Hardware Translation: Translate workload analysis and research findings into hardware specifications. Identify where architectural innovation creates the most leverage, define the structures that realize it, and produce microarchitecture documents unambiguous enough for RTL engineers to implement against. You work closely with them through implementation, not over the wall from it. - Full-Stack PPA Tradeoffs: Reason across the full stack and defend PPA tradeoffs at every level. Move between algorithm-level workload behavior, memory hierarchy, on-chip interconnect, and physical design constraints. Make the call when the data is incomplete, and articulate why under scrutiny from our Systems Architect and the research team. - ISA Co-Design: Partner with the compiler lead on ISA co-design. The compute tile must be compilable and programmable, not just simulatable. The programming model and the microarchitecture are defined together, and you are accountable for both sides meeting in the middle. - Prototyping Strategy: Direct block-level pre-silicon validation. Decide which microarchitecture questions are answered in FPGA versus cycle-accurate simulation, define what each prototype must prove, and partner with our FPGA Design Engineer, who owns implementation and bring-up, to de-risk decisions before tapeout. System-level validation is owned by our Systems Architect. - Research Fluency: Stay current with the AI accelerator research landscape and be able to articulate clearly where Normal's approach differs from existing solutions and why that matters. This is a research-adjacent seat and you are expected to read, not just consume. WHAT MAKES YOU A GREAT FIT - A degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent work experience. PhD welcome but not required; the bar is the work, not the credential. - Substantial experience in architecture or microarchitecture of high-performance digital systems: AI accelerators, compute engines, or similarly complex logic. You have shaped the structures inside a chip, not just consumed them from the outside. - Fluency moving between algorithm-level analysis and hardware specification. You can read a profile of a workload and translate it into datapath widths, pipeline stages, and area/power estimates without losing the thread on either side. - Experience with simulation-driven architecture. You have used cycle-accurate or analytical models to make and defend design decisions before RTL exists, and you know which questions each tool can answer and which it cannot. - Familiarity with quantization and reduced-precision approaches for inference and their implementation implications. You understand the cost of a bit at the hardware level, not just the model level. - Experience writing microarchitecture specifications and working closely with RTL engineers through implementation. Your s