Senior FPGA Verification Engineer

Anduril Industries is a defense technology company with a mission to transform U.S. and allied military capabilities with advanced technology. By bringing the expertise, technology, and business model of the 21st century’s most innovative companies to the defense industry, Anduril is changing how military systems are designed, built and sold. Anduril’s family of systems is powered by Lattice OS, an AI-powered operating system that turns thousands of data streams into a realtime, 3D command and control center. As the world enters an era of strategic competition, Anduril is committed to bringing cutting-edge autonomy, AI, computer vision, sensor fusion, and networking technology to the military in months, not years. ABOUT THE TEAM The Air Dominance and Strike (AD&S) Electrical Engineering Team develops high-reliability avionics, embedded processing, and power systems for Group 5 air vehicles and missile platforms. The team delivers flight-critical electronics, PCB assemblies, and FPGA-based processing architectures for Anduril’s next-generation autonomous air platforms. AD&S Electrical Engineers drive end-to-end development, from system architecture and circuit design to verification, integration, and flight test. Solutions must be scalable, mission-ready, and meet the performance, reliability, and survivability demands of modern air warfare. ABOUT THE JOB We are looking for a Senior FPGA Verification Engineer to join our rapidly growing team in Costa Mesa, CA. You will lead verification strategy and methodology for FPGA/SoC designs on AMD (Xilinx) platforms for flight-critical avionics, owning UVM-based methodology, coverage-driven verification, and the roadmap for verification tooling across our programs. You will set technical direction for the verification team and mentor other engineers while partnering closely with design, systems, and program leadership. If you have led verification closure on production avionics or flight programs and want to shape how a growing team works, this role is for you. WHAT YOU’LL DO Define UVM architecture and reusable verification component libraries used across programs Mentor verification engineers by reviewing testbenches, verification plans, and coverage models Represent verification in design reviews and program milestones Drive verification tooling, CI/CD, and regression infrastructure roadmap for the team Architect UVM verification environments (drivers, monitors, predictors, scoreboards) for AMD (Xilinx) FPGA/SoC designs and establish patterns others on the team follow Develop verification plans with traceability to system and hardware requirements Author SystemVerilog Assertions (SVA) for protocol compliance and design intent checks Build functional coverage models and drive code coverage analysis to closure Develop constrained-random and transaction-level test sequences to maximize coverage and uncover corner-case bugs Establish and maintain regression suites, tracking coverage metrics and verification progress Debug failures using waveform tools and simulation logs at the HDL and system level Collaborate with design engineers on RTL reviews, bug resolution, and micro-architecture refinement Support hardware validation and board bring-up on target platforms Ensure verification meets DO-254 and relevant safety standards Author verification closure reports and coverage analysis summaries REQUIRED QUALIFICATIONS Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field 7+ years of experience in FPGA/ASIC verification Proficient in SystemVerilog, UVM methodology and SVA, with experience contributing to and extending UVM testbenches Object-oriented programming principles Industry simulators (Questa, VCS, Xcelium, or Vivado) Git-based collaborative workflows including code review Linux development environments SVUnit or equivalent unit-testing frameworks Formal verification or CDC verification tools Verification automation scripting (Python, Tcl, Makefile) Track record owning verification closure on a production or flight program end-to-end Experience defining verification methodology and mentoring engineers Strong communication and teamwork skills Eligible to obtain and hold a U.S. Secret security clearance PREFERRED QUALIFICATIONS 10+ years of experience in FPGA/ASIC verification Master’s degree in Electrical Engineering, Computer Engineering, or related field DO-254, avionics verification standards for UAS, and safety-critical verification processes Digital interfaces: Ethernet, PCIe, JESD204C, MIL-STD-1553, SPI SoC and ARM-based embedded platforms Verification automation, CI/CD integration, and Nix-based build environments UVM base-class and framework library development DO-254 DAL A/B artifact ownership and experience supporting DER or customer audits US Salary Range $146,000 — $194,000 USD The salary range for this role is an estimate based on a wide range of comp